Previous logic systems, such as synchronous boolean logic systems, have employed clocking signals to regulate the sequential processing of binary logic signals. Typically, a combinational logic circuit will respond to multiple inputs to generate an output. As input logic signals propagate through the combinational circuit, the circuit output in unreliable for a period of time corresponding to set-up times and variations in propagation delays through the individual logic gates. Typically, the output signal is sampled at a time when the output is stable, often by latching the output into a register. The sampling is controlled by an independent clock signal, i.e., one that is not derived from the states of the logic gates themselves.
While these traditional synchronous circuits have become widely used, a substantial amount of design analysis is necessary to avoid a variety of timing-related problems, such as race conditions. Designers must build in timing margin to ensure that combination circuit outputs are stable, but this additional margin results in circuits operating at less than maximum speed. In addition, the fraction of power and wafer surface area that must be devoted to clocking circuitry is substantially, and in certain instances, may limit the total amount of circuitry that can be integrated onto a single chip.